課題番号 ：S-20-SH—0002
利用形態 ：共同研究型支援
利用課題名（日本語） ：酸化物系エレクトロニクスデバイス（メモリスタ、FET、センサー、など）の開発
Program Title (English) ：Development of oxide based electronic devices such as memristor, FET, sensors, etc.
利用者名（日本語） ：シャイバル　ムカジー
Username (English) ：SHAIBAL MUKHERJEE
所属名（日本語） ：インド工科大学、インドール校
Affiliation (English) ：Indian Institute of Technology Indore (IITI)

１．概要（Summary ）
In 2020 fiscal year, three categories such as detailed analyses on Y2O3 based memristors, ZnO based multiple-quantum-well (MQW) structures, and heterojunction field effect transistor (HFET), were carried out successfully. In the first, the results of investigation on the impact of interfacial SiO2 layer in the Y2O3-based memristive system were described [1]. In the second, the results of analyses on CdZnO/ZnO-based MQW for photovoltaic application were reported [2]. In the third, a technique to optimize the drain current in MgZnO/CdZnO HFET was discussed [3].

２．実験（Experimental）
The following facilities of Shinshu University such as high-resolution TEM (JOEL JEM2100, Hitachi STEM (HD2300A), and STM (Unisoku) were utilized for the detailed analyses of the devices, which were fabricated at the Indian Institute of Technology Indore (IITI).

３．結果と考察（Results and Discussion）
In Fig. 1(a), the cross-sectional TEM image of Y2O3-based memristor is shown, where formation of SiO2 is clearly confirmed. It is found that the effect of thickening of SiO2 layer is extremely detrimental for resistive switching (RS) parameters such as endurance and uniformity of current-voltage characteristics of the memristors. In Fig. 1(b), the cross-sectional TEM image of CdZnO/ZnO-based MQW structures is shown overlaid with its chemical composition. The deposition of MQW structure performed at 100 oC, with time cessation of 30 min between successive layer growth and ion beam power of 14 W has displayed the best results in terms of distinct well and barrier layers formation. In Fig. 1(c), the
cross-sectional TEM image of the MgZnO/CdZnO HFET is shown along with its SAED pattern. The results suggest that introduction of yttria spacer layer improves the overall conductance up to 3.5 × 1015 　V-1s-1 as compared to 9 × 1014 V-1s-1 of non-yttria spacer device.

４．その他・特記事項（Others）
なし。

５．論文・学会発表（Publication/Presentation）
M. Das, A. Kumar, et al, Impact of Interfacial SiO2 on Dual Ion Beam Sputtered Y2O3-based Memristive System, IEEE Trans. Nanotechnology,19:332 – 337, 2020.
G. Siddharth, et al, Investigation of DIBS-deposited CdZnO/ZnO-based Multiple Quantum Well for Large-area Photovoltaic Application, IEEE Trans. Electron Devices,67(12):5587-5592, 2020.
M. A. Khan, et al, Drain Current Optimization in DIBS-grown MgZnO/CdZnO HFET, IEEE Trans. Electron Devices,67(6):2276-2281, 2020.